SRAMs (static random access memories) are memory elements that store data in the form of complementary low voltage and high voltage at opposite sides of the SRAM. An SRAM, unlike dynamic random access memory (DRAM), maintains the memory value all of the time that power is applied to the circuit. This is unlike the DRAM, which is periodically refreshed with the value to be saved. If the “true” node is read as a high voltage, the value of the SRAM is one. If the true polarity node is read as a low voltage, the value of the SRAM is zero.
Within some SRAMs, there are individualized write true (WriteT) lines and write complementary (WriteC) lines that are used to write complementary values to the complementary polarity nodes inside. However, it was discovered that the separate WriteC bitline to each individual SRAM cell could be replaced by a continuous bit-line complementary (BLC) to all of the SRAMs cells along the same bitline. A bitline can generally be defined as a connection to a plurality of SRAM cells at a transfer gate.
However, as processing speeds increase and devices within integrated circuits become ever smaller, the complexity of the SRAM cell, and power consumption of the SRAM are of ever-increasing concern. Even though use of the continuous BLC line within an SRAM cell has reduced some of the complexity of the local evaluator, these issues are still of concern to chip designers.
Therefore, there is a need for an SRAM design that overcomes at least some of the issues associated with conventional SRAM design.